EN29F040-45J Ver la hoja de datos (PDF) - Eon Silicon Solution Inc.

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EN29F040-45J

4 Megabit (512K x 8-bit) Flash Memory

Eon Silicon Solution Inc. 

EN29F040

DATA PROTECTION

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even

with CE = VIL, W E = VIL and OE = VIH, the device will not accept commands on the rising edge of

WE.

Low VCC Write Inhibit

During VCC power-up or power-down, the EN20F040 locks out write cycles to protect against any

unintentional writes. If VCC < VLOK, the command register is disabled and all internal program or

erase circuits are disabled. Under this condition, the device will reset to the READ mode. Subsequent

writes will be ignored until VCC > VLKO.

Write “Noise” Pulse Protection

Noise pulses less than 5ns on OE , CE or WE will neither initiate a write cycle nor change the

command register.

Logical Inhibit

If CE =VIH or WE=VIH, writing is inhibited. To initiate a write cycle, CE and W E must be a logical

“zero”. If CE , W E , and OE are all logical zero (not recommended usage), it will be considered a

write.

Sector Protect and Unprotect

The hardware sector protection feature disables both program and erase operations in any sector.

The hardware sector unprotection feature re-enables both program and erase operation in previously

protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure

requires a high voltage (VID) on address pin A9 and the control pins. Contact Eon Silicon Devices,

Inc. for an additional supplement on this feature.

4800 Great America Parkway, Suite 202

14

Santa Clara, CA 95054

Rev. D, Issue Date: 2001/07/05

Tel: 408-235-8680

Fax: 408-235-8685

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