MT4LC4M16R6TG-6S Ver la hoja de datos (PDF) - Micron Technology

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MT4LC4M16R6TG-6S

4 MEG x 16 EDO DRAM

Micron Technology 

NOTES (continued)

28. Output parameter (DQx) is referenced to

corresponding CAS# input; DQ0-DQ7 by CASL#

and DQ8-DQ15 by CASH#.

29. Each CASx# must meet minimum pulse width.

30. The last CASx# edge to transition HIGH.

31. Last falling CASx# edge to first rising CASx#

edge.

32. Last rising CASx# edge to first falling CASx#

edge.

33. Last rising CASx# edge to next cycle’s last rising

CASx# edge.

34. Last CASx# to go LOW.

4 MEG x 16

EDO DRAM

35. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse

width ≤ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. VIL

undershoot: VIL (MIN) = -2V for a pulse width ≤

3ns, and the pulse width cannot be greater than

one third of the cycle rate.

36. NC pins are assumed to be left floating and are

not tested for leakage.

37. Self refresh and extended refresh for either device

requires that at least 4,096 cycles be completed

every 128ms.

4 Meg x 16 EDO DRAM

D29_2.p65 – Rev. 5/00

12

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000, Micron Technology, Inc.

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