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FAN6920MR

Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller

Fairchild Semiconductor 

VDD-ON

VDD-PWM-OFF

VDD-OFF

Gate

IDD-OP

IDD-PWM-OFF IDD-ST

Figure 39. Typical Waveform of VDD Voltage and

Gate Signal at Hiccup Mode Operation

Green-Mode Operation and PFC-ON / OFF Control

(FB Pin)

Green mode further reduces power loss in the system

(e.g. switching loss). Through off-time modulation to

regulate switching frequency according to FB pin

voltage. When output loading decreases, FB voltage

lowers due to secondary feedback movement and the

tOFF-MIN is extended. After tOFF-MIN (determined by FB

voltage), the internal valley-detection circuit is activated

to detect the valley on the drain voltage of the PWM

switch. When the valley signal is detected, FAN6920MR

outputs a PWM gate signal to turn on the switch and

begin a new switching cycle.

With green mode operation and valley detection, at

light-load condition; the power system can perform

extended valley switching a DCM operation and can

further reduce switching loss for better conversion

efficiency. The FB pin voltage versus tOFF-MIN time

characteristic curve is shown in Figure 40. As Figure 40

shows, FAN6920MR can narrow down to 2.25ms tOFF

time, which is around 440Hz switching frequency.

Referring to Figure 1 and Figure 2, FB pin voltage is not

only used to receive secondary feedback signal to

determine gate on-time, but also determines PFC stage

operating mode.

Figure 40. VFB Voltage vs. tOFF-MIN Time

Characteristic Curve

Valley Detection (DET Pin)

When FAN6920MR operates in green mode, tOFF-MIN is

determined by the green-mode circuit according to FB

pin voltage level. After tOFF-MIN, the internal valley-

detection circuit is activated. During tOFF of the PWM

switch, when transformer inductor current discharges to

zero, the transformer inductor and parasitic capacitor of

© 2010 Fairchild Semiconductor Corporation

FAN6920MR • Rev. 1.0.3

PWM switch start to resonate concurrently. When the

drain voltage on the PWM switch falls, the voltage

across on auxiliary winding VAUX also decreases since

auxiliary winding is coupled to primary winding. Once

the VAUX voltage resonates and falls to negative, VDET

voltage is clamped by the DET pin (refer to Figure 41)

and FAN6920MR is forced to flow out a current IDET.

FAN6920MR reflects and compares this IDET current. If

this source current rises to a threshold current, PWM

gate signal is sent out after a fixed delay time (200ns

typical).

Figure 41. Valley Detection

VAUX

0V

VDET

0V

OPWM

tOFF

Start to

Idet flow out

detect valley from DET pin

Delay time and

then trigger

gate signal

Valley

switching

Figure 42. Measured Waveform of Valley Detection

High / Low Line Over-Power Compensation (DET Pin)

Generally, when the power switch turns off, there is a

delay from gate signal falling edge to power switch off.

This delay is produced by an internal propagation delay

of the controller and the turn-off delay of the PWM

switch due to gate resistor and gate-source capacitor

CISS. At different AC input voltages, this delay produces

different maximum output power with the same PWM

current limit level. Higher input voltage generates higher

maximum output power because applied voltage on

primary winding is higher and causes higher rising slope

inductor current. It results in higher peak inductor

current at the same delay. Furthermore, under the same

output wattage, the peak switching current at high line is

lower than that at low line. Therefore, to make the

maximum output power close at different input voltages,

the controller needs to regulate VLIMIT voltage of the

CSPWM pin to control the PWM switch current.

Referring to Figure 1, during tON of the PWM switch, the

input voltage is applied to primary winding and the

voltage across on auxiliary winding VAUX is proportional

to primary winding voltage. As the input voltage

increases, the reflected voltage on auxiliary winding

VAUX becomes higher as well. FAN6920MR also clamps

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