FAN6920 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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Fabricante

FAN6920

Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller

Fairchild Semiconductor 

Functional Description

PFC Stage

Multi-Vector Error Amplifier and THD Optimizer

For better dynamic performance, faster transient

response, and precise clamping on the PFC output,

FAN6920MR uses a transconductance type amplifier

with proprietary innovative multi-vector error amplifier

(US Patent 6,900,623). The schematic diagram of this

amplifier is shown in Figure 25. The PFC output voltage

is detected from the INV pin by an external resistor

divider circuit that consists of R1 and R2. When PFC

output variation voltage reaches 6% over or under the

reference voltage of 2.5V, the multi-vector error

amplifier adjusts its output sink or source current to

increase the loop response to simplify the compensated

circuit.

PFC RS

MOS Filp-Flop

VCOMP

RS

4

THD +

Optimizer

CSPFC



+

Sawtooth

Generator

Error

Amplifier

PFC VO

2.5V R1

3

INV

R2

FAN6920MR

Figure 26. Multi-Vector Error Amplifier with

THD Optimizer

Figure 25. Multi-Vector Error Amplifier

The feedback voltage signal on the INV pin is compared

with reference voltage 2.5V, which makes the error

amplifier source or sink current to charge or discharge

its output capacitor CCOMP. The COMP voltage is

compared with the internally generated sawtooth

waveform to determine the on-time of PFC gate.

Normally, with lower feedback loop bandwidth, the

variation of the PFC gate on-time should be very small

and almost constant within one input AC cycle.

However, the power factor correction circuit operating at

light-load condition has a defect, zero crossing

distortion; which distorts input current and makes the

system’s Total Harmonic Distortion (THD) worse. To

improve the result of THD at light-load condition,

especially at high input voltage, an innovative THD

optimizer (US Patent 7,116,090) is inserted by sampling

the voltage across the current-sense resistor. This

sampling voltage on current-sense resistor is added into

the sawtooth waveform to modulate the on-time of PFC

gate, so it is not constant on-time within a half AC cycle.

The method of operation block between THD optimizer

and PWM is shown in Figure 26. After THD optimizer

processes, around the valley of AC input voltage, the

compensated on-time becomes wider than the original.

The PFC on-time, which is around the peak voltage, is

narrowed by the THD optimizer. The timing sequences

of the PFC MOS and the shape of the inductor current

are shown in Figure 27. Figure 28 shows the difference

between calculated fixed on-time mechanism and fixed

on-time with THD optimizer during a half AC cycle.

Figure 27. Operation Waveforms of Fixed On-Time

with and without THD Optimizer

Figure 28. Calculated Waveforms of Fixed On-Time

with and without THD Optimizer During a Half

AC Cycle

© 2010 Fairchild Semiconductor Corporation

FAN6920MR • Rev. 1.0.3

16

www.fairchildsemi.com

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