FAN2560(2008) Ver la hoja de datos (PDF) - Fairchild Semiconductor

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Fabricante

FAN2560
(Rev.:2008)

350mA Low-VIN LDO with Fast Transient Response

Fairchild Semiconductor 

Block Diagram

Figure 3. IC Block Diagram

Pin Configuration

VIN A1 A3 VOUT

GND B2

VBAT C1 C3 EN

VOUT A3 A1 VIN

B2 GND

EN C3 C1 VBAT

TOP VIEW

BOTTOM VIEW

Figure 4. 0.96 x 1.33mm WLCSP package

Pin Definitions

Pin #

A1

A3

C1

C3

B2

Name

VIN

VOUT

VBAT

EN

GND

Description

Power supply input. A minimum 1μF MLCC is required to GND.

Output Voltage. A typical COUT=1μF to 2.2μF MLCC is required to GND, placed close to the

VOUT terminal.

Battery bias supply input. No capacitor is required unless another bulk capacitor is more than

few inches away.

Enable input. The device is in shutdown mode when the voltage at this pin is <0.4V and

enabled when >1.1V. The EN latches the LOW logic state once externally forced. Do not leave

this pin floating when the device is turned ON.

Ground pin. Connect to a PCB GND plane.

© 2006 Fairchild Semiconductor Corporation

FAN2560 • Rev. 1.0.0

2

www.fairchildsemi.com

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