EPM5032-15 Ver la hoja de datos (PDF) - Altera Corporation

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EPM5032-15

Programmable Logic Device Family

Altera Corporation 

MAX 5000 Programmable Logic Device Family Data Sheet

Figure 7. MAX 5000 Timing Model

Single-LAB EPLDs

Input

Delay

tIN

I/O

Delay

tIO

Shared Expander

Delay

tSEXP

Logic Array

Control Delay

tLAC

Logic Array

Delay

tLAD

Global

Clock Delay

tICS

Array Clock

Delay

tIC

Register

Delay

tRD

tCOMB

tLATCH

tCLR

tPRE

tSU

tH

Feedback

Delay

tFD

Output

Delay

tOD

tXZ

tZX

Multi-LAB EPLDs

Input

Delay

tIN

PIA

Delay

tPIA

Shared Expander

Delay

tSEXP

Logic Array

Control Delay

tLAC

Logic Array

Delay

tLAD

Global Clock

Delay

tICS

Register

Delay

tRD

tCOMB

tLATCH

tCLR

tPRE

tSU

tH

Array Clock

Delay

tIC

I/O

Delay

tIO

Feedback

Delay

tFD

Output

Delay

tOD

tXZ

tZX

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