EPL09060 Ver la hoja de datos (PDF) - ELAN Microelectronics
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EPL09060 Datasheet PDF : 54 Pages
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EPL09060
9 COM/60 SEG LCD Driver
7 Functional Description
Bus Holder
Instruction
Decoder
Instruction
Register
Status
Register
MPU Interface
I/O Buffer
( Serial/Parallel )
/CS1 CS2 A0 /RD /WR C86 P/S /RES D7 D6 D5 D4 D3 D2 D1 D0 BUSY
(E) (R/W)
(SDI)(SCK)(SDO)
Figure 3 System Interface
7.1 MPU Interface
7.1.1 Chip Select
The EPL09060 has two chip select pins /CS1 and CS2. When /CS1="L" and
CS2=”H”, MPU interface is available. When the chip select pin is inactive (other /CS1
and CS2 condition), D7 to D0 are high impedance (invalid) and input of A0, /RD, or
/WR inputs are not effective. If serial interface is selected, the shift register and the
counter are both reset. However, reset is always operated in any conditions of /CS1
and CS2.
P/S
C86
A0
WR
/RD D0~D4 D5
D6
D7
Serial
Mode
SPI interface
(−)
A0
R/W
−
(L)
*
SDO SCK SDI
Parallel 80-series (L) A0
Mode
(H) 68-series (H) A0
/WR
/RD
R/W
E
D0~D7
D0~D7
Note: “ * ” Don’t care (“High”, “Low” or “Open”)
“−” Indicates that it is fixed to either “High” (VDD) or “Low” (VSS)
12 •
Product Specification (V1.0) 12.28.2005
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