0 0101 00rr rrrr 05rr INCA R
0 0101 01rr rrrr 05rr INC R
0 0101 10rr rrrr 05rr DJZA R
0 0101 11rr rrrr 05rr DJZ R
0 0110 00rr rrrr 06rr RRCA R
0 0110 01rr rrrr 06rr RRC R
0 0110 10rr rrrr 06rr RLCA R
0 0110 11rr rrrr 06rr RLC R
0 0111 00rr rrrr 07rr SWAPA R
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
1 00kk kkkk kkkk
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
1 1100 kkkk kkkk
1 1101 kkkk kkkk
1 1110 0000 0001
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E01
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
1 1110 100k kkkk
1 1111 kkkk kkkk
1E8k
1Fkk
PAGE k
ADD A,k
** 1 Instruction cycle = 2 main CLK
EM78P5840/5841/5842
8-bit Micro-controller
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1)
R(0) → C, C → A(7)
R(n) → R(n-1)
R(0) → C, C → R(7)
R(n) → A(n+1)
R(7) → C, C → A(0)
R(n) → R(n+1)
R(7) → C, C → R(0)
R(0-3) → A(4-7)
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP]
(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP]
001H → PC
K->R5(4:0)
k+A → A
Z
Z
None
None
C
C
C
C
None
None
None
None
None
None
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
None
Z,C,DC
1
1
2 if skip
2 if skip
1
1
1
1
1
1
2 if skip
2 if skip
1
1
2 if skip
2 if skip
2
2
1
1
1
1
2
1
1
1
1
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
29
2004/11/10 V2.6