EM78P159N
8-Bit Microcontroller with OTP ROM
C.2 Power-On Reset and Vdd Voltage Drop/Rise Timing Test
Vdd
/Reset
Internal POR
Power on
Reset
Tpor
Tvr
Tvd
Symbol
Tpor
Tvd*
Tvr**
Parameter
Power on reset time
Vdd Voltage drop time
Vdd Voltage rise time
Condition
Vdd = 5V, -40℃ to 85℃
Vdd = 5V, -40℃ to 85℃
Vdd = 5V, -40℃ to 85℃
Min. Typ. Max. Unit
10.5 16.8
22
ms
-
-
1
µs
-
-
1
us
* Tvd is the period of Vdd voltage lower than POR voltage.
** Tvr is the period of Vdd voltage higher than 5.5V.
Figure C-1 EM78P159N Power-On Reset and Vdd Voltage Drop/Rise Timing Test Timing Diagram
C.3 Address Trap Detect
An address trap detect is one of the fail-safe function that detects CPU malfunction
caused by noise or the like. If the CPU attempts to fetch an instruction from a part of
RAM, an internal recovery circuit will be auto started. Until CPU got the correct
function, it will execute the next program.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
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