EM78910A Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM78910A Datasheet PDF : 30 Pages
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EM78910/910A
8-bit Micro-controller
:
MOV 0X05,A
:
SWAPA R3_BUFFER ;Return R3
:
MOV 0X03,A
:
SWAPA A_BUFFER ;Return ACC
:
RETI
VII.7 Instruction Set
Instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O
register.
The symbol "R" represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit,
located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
HEX
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 0010 0000
0014
001r
0020
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
TBL
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2 bits 9,10 do not
clear
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A∨R→A
A∨R→R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
STATUS
AFFECTED
None
C
None
T,P
T,P
None
None
None
None
None
None
None
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
~ 17~
2001/01/12
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