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EM78910 Ver la hoja de datos (PDF) - ELAN Microelectronics

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componentes Descripción
Fabricante
EM78910
EMC
ELAN Microelectronics EMC
EM78910 Datasheet PDF : 30 Pages
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EM78910/910A
8-bit Micro-controller
* Bit 5 (/WUP9H) : PORT9’s high nibble wakeup control, 1/0 ! enable/disable
It is used to enable the wakeup function of high nibble for PORT9.
* Bit 6 (/WDTE) : Watchdog timer control, 1/0 ! enable/disable
It is used to enable/disable Watchdog timer.
The relation between Bit3 to Bit6 can see the diagram 9.
* Bit 7(CWPWR) : Power control of Call waiting circuit, 1/0 ! power up circuit /power down circuit
When Call waiting circuit is powered on, PLL is also enabled regardless of RA bit 6(ENPLL). When Call
waiting circuit is powered off, PLL status is depended on RA bit 6 (ENPLL) setting.
/WURING
/RINGTIME
/WUP9L
PORT9(3:0)
/WUP9H
PORT9(7:4)
/WDTE
/WDTEN 0/1=enable/disable
Fig.9 Wake up function and control signal
14. RF (Interrupt status register)
7
6
5
4
321
0
INT3
FSK/CW C8_2 C8_1 INT2 INT1 INT0 TCIF
* Bit 0 (TCIF) : TCC timer overflow interrupt flag. Set when TCC timer overflows.
* Bit 1 (INT0) : External INT0 pin interrupt flag
* Bit 2 (INT1) : External INT1 pin interrupt flag
* Bit 3 (INT2) : External INT2 pin interrupt flag
* Bit 4 (C8_1) : Internal 8 bit counter interrupt flag
* Bit 5 (C8_2) : Internal 8 bit counter interrupt flag
* Bit 6 ( FSK/CW ) : FSK data or Call waiting data interrupt flag
* Bit 7 (INT3) : External INT3 pin interrupt flag.
High to low edge trigger. Refer to the Interrupt subsection.
IOCF is the interrupt mask register. User can read and clear.
"1" means interrupt request, "0" means non-interrupt
15. R10~R3F (General Purpose Register)
* R10~R3F (Banks 0~3) are all general-purpose registers.
VII.2 Special Purpose Registers
1. A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
2. CONT (Control Register : P70 interrupt edge, INT flag, TCC edge, precaler rate selection for TCC or WDT )
7
6
5
4
3
2
1
0
INT_EDGE INT TS TE PAB PSR2 PSR1 PSR0
* Bit 2~0 (PSR2~PSR0) : TCC/WDT prescaler bits.
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
~ 10~
2001/01/12

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