EM78871AQ Ver la hoja de datos (PDF) - ELAN Microelectronics
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Fabricante
EM78871AQ Datasheet PDF : 59 Pages
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EM78871
8-bit Micro-controller
SPIE
Read
R5
RBF RBFI
set to 1
SPIR reg.
Buffer Full Detector
SPIWC
Write
R5
SPIW reg.
S D I/ P 6 2
MUX
SDI
PORT62
SPIS reg.
shift right
bit 0
bit 7
SDO/P61
MUX
SDO
PORT61
SPIC reg. (R4 page1)
SPIE
0
3
SBR0 ~SBR2
Tsco
Prescaler
4, 8, 16, 32, 64, 128
16.38kHz
SBR2~SBR0
2
3
Clock Select
Edge
Select
SCK
Edge
Select
N o ise
Filter
SCK
PORT60
MUX
SPIE
SCK/P60
Fig.7 SPI structure
SPIC reg. : SPI control register
SDO/P61 : Serial data out
SDI/P62 : Serial data in
SCK/P60 : Serial clock
RBF : Set by buffer full detector, and reset in software.
RBFI : Interrupt flag. Set by buffer full detector, and reset in software.
Buffer Full Detector : Sets to 1, while an 8-bit shifting is complete.
SE : Loads the data in SPIW register, and begin to shift
SPIE : SPI control register
SPIS reg. : Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the SPIW register are
loaded at the same time. Once data being written to, SPIS starts transmission / reception. The received data
will be moved to the SPIR register, as the shifting of the 8-bit data is complete. The RBF (Read Buffer Full )
flag and the RBFI(Read Buffer Full Interrupt) flag are set.
SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is complete. The data must be read before the
next reception is finished. The RBF flag is cleared as the SPIR register read.
SPIW reg. : Write buffer. The buffer will deny any write until the 8-bit shifting is complete. The SE bit will be kept in 1
if the communication is still under going. This flag must be cleared as the shifting is finished. Users can
determine if the next write attempt is available.
SBR2 ~ SBR0: Programming the clock frequency/rates and sources.
Clock select : Selecting either the internal instruction clock or the external 16.338KHz clock as the shifting clock.
Edge Select : Selecting the appropriate clock edges by programming the SCES bit
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* This specification is subject to be changed without notice. 15
8/23/04 (V1.5)
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