EM78815 Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM78815 Datasheet PDF : 82 Pages
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EM78815
8-Bit Microcontroller
6.5 DTMF Receiver, OP
Pin
I/O
EST
O
STGT
I/O
Description
Early steering output. Presents a logic high immediately
when the digital algorithm detects a recognizable tone-pair
(signal condition). Any momentary loss of signal condition
will cause the EST to return to a logic low. This is pin-
shared with Port 61.
Steering input/guard time output (bi-directional). A voltage
greater than Vtst detected at ST causes the device to
register the detected tone-pair and update the output latch.
A voltage less than Vtst frees the device to accept a new
tone-pair. The GT output acts to reset the external steering
time-constant; its state is a function of EST and the voltage
on ST. This is pin-shared with Port 60.
6.6 Serial IO, Comparator, Current DA, Tone
Pin
SCK
SDO
SDI
UR
UT
CMP1
CMP2
CMP3
DAOUT
KTONE
TONE
I/O
Description
I/O
Master: output pin, Slave: input pin. This is pin-shared with
Port D4.
O
Output pin for serial data transferring. This is pin-shared with
Port D5.
I
Input pin for receiving data. This is pin-shared with Port D6.
I
Data receiver pin for UART. This pin shared with Port D2
O
Data transmitter pin for UART. This is pin-shared with Port D3.
I
Comparator input pins. This is pin-shared with Port 65.
I
Comparator input pins. This is pin-shared with Port 66
I
Comparator input pins. This is pin-shared with Port 67.
O
Current DA output pin. It can be a control signal for sound
generation. This is pin-shared with Port D7.
O
Key tone output. This is pin-shared with Port 76.
O
Dual tone output pin
6.7 IO
Pin
P60 ~P67
P70 ~ P77
P80 ~ P87
P90 ~ P97
PB0 ~ PB7
PC0 ~ PC7
PD0 ~ PD7
P70 ~ P76
P77
/RESET
I/O
Description
I/O
Each bit in Port 6 can be Input or Output port.
Internal pull high.
Each bit in Port 7 can be Input or Output port.
I/O
Internal Pull high function, Auto key scan function, and
Interrupt function.
I/O
Each bit in Port 8 can be Input or Output port.
I/O
Each bit in Port 9 can be Input or Output port.
I/O
Each bit in Port B can be Input or Output port.
I/O
Each bit in Port C can be Input or Output port.
I/O
Each bit in Port D can be Input or Output port.
This is pin-shared with SPI pin and CMP input pin.
Interrupt sources. When any pin from Port 70 to Port 76
I
has a falling edge signal, it will generate a corresponding
interrupt.
Interrupt source. Once Port 77 has a falling edge or rising
I
edge signal (controlled by CONT register), it will generate
an interrupt.
I
Low reset
8•
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
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