EL5421T Ver la hoja de datos (PDF) - Intersil
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EL5421T Datasheet PDF : 13 Pages
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EL5421T
phase margin and the stability of the EL5421T. The
advantage of a snubber circuit is that it does not draw any
DC load current or reduce the gain.
Another method to reduce peaking is to add a series output
resistor (typically between 1Ω to 10Ω). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
Power Dissipation
With the high-output drive capability of the EL5421T buffers,
it is possible to exceed the +150°C absolute maximum
junction temperature under certain load current conditions. It
is important to calculate the maximum power dissipation of
the EL5421T in the application. Proper load conditions will
ensure that the EL5421T junction temperature stays within a
safe operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
PDMAX = T----J---M-----A----X-Θ----–-J---A-T----A---M-----A----X--
(EQ. 1)
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• ΘJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the loads,
or:
PDMAX = Σi[V S × ISMAX + (V S+ – VOUTi ) × ILOADi ] (EQ. 2)
when sourcing, and:
PDMAX = Σi[VS × ISMAX + (VOUTi – VS- ) × ILOADi ]
(EQ. 3)
when sinking.
Where:
• i = 1 to 4
(1, 2, 3, 4 corresponds to Channel A, B, C, D respectively)
• VS = Total supply voltage (VS+ - VS-)
• VS+ = Positive supply voltage
• VS- = Negative supply voltage
• ISMAX = Maximum supply current per buffer
(ISMAX = EL5421T quiescent current ÷ 4)
• VOUT = Output voltage
• ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in the
highest power dissipation. To find RLOAD set the two PDMAX
equations equal to each other and solve for VOUT/ILOAD.
Reference the package power dissipation curves, Figures 27
and 28, for further information.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
8
7 625mW
6
5
MSOP10
θJA = +200°C/W
4
3
2
1
0
0
25
50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE
1.0 THERMAL CONDUCTIVITY TEST BOARD
0.9
781mW
0.8
0.7
0.6
MSOP10
θJA = +160°C/W
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
11
FN6922.0
September 25, 2009
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