EDS2516APTA Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EDS2516APTA

256M bits SDRAM

Elpida Memory, Inc 

EDS2516APTA

Current state

/CS /RAS /CAS /WE Address

Command

Operation

Mode register set

H

×

×

×

×

DESL

NOP

L

H

H

H

×

NOP

NOP

L

H

H

L

×

BST

ILLEGAL

L

H

L

H

BA, CA, A10 READ/READA

ILLEGAL*4

L

H

L

L

BA, CA, A10 WRIT/WRITA

ILLEGAL*4

L

L

H

H

BA, RA

ACT

Bank and row active*9

L

L

H

L

BA, A10

L

L

L

H

×

L

L

L

L

MODE

PRE, PALL

REF, SELF

MRS

NOP

Refresh*9

Mode register set*8

ERemark: H: VIH. L: VIL. ×: VIH or VIL

Notes: 1.An interval of tDPL is required between the final valid data input and the precharge command.

2. If tRRD is not satisfied, this operation is illegal.

3. Illegal for same bank, except for another bank.

O4. Illegal for all banks.

5. NOP for same bank, except for another bank.

6. Illegal if tRCD is not satisfied.

L7. Illegal if tRAS is not satisfied.

8. MRS command must be issued after DOUT finished, in case of DOUT remaining.

Product 9. Illegal if lMRD is not satisfied.

Data Sheet E0359E20 (Ver. 2.0)

21

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