EB381D Ver la hoja de datos (PDF) - Motorola => Freescale

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EB381D

Migrating from the MC68HC811E2 to the MC68HC11F1

Motorola => Freescale 

Freescale Semiconductor, Inc.

Engineering Bulletin

• For the CSGEN chip select, the G1SZA–G1SZC bits in the

CSGSIZ register ($105F) must be programmed to %011 for an 8-

Kbyte RAM or to %010 for a 16-Kbyte RAM.

– Next, the starting address for this address must be

programmed. This is done by programming bits GA13 and

GA15 for the 8-Kbyte RAM or bits GA14 and GA15 for the

16-Kbyte RAM. Like the CSPROG, clear the GSTHA and

GSTHB bits to disable the clock stretch.

– The user should also set the GNPOL bit (bit 4) in the CSGSIZ

register to a 0 to make sure chip select CSGEN is an active

low. Normally, the chip select for an external RAM device is

made active with respect to the E clock going high. In this

example, the CSGEN chip select needs to be made active

during the address valid time. This is done by setting the

GAVLD bit (bit 3) in the CSGSIZ register to a 1.

– The user should also check the other options available in the

CSGSIZ register.

EB381

14

MOTOROLA

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