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DSP56311 Datasheet PDF : 96 Pages
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AC Electrical Characteristics
2.4.4 Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6
No.
Characteristics
Expression
150 MHz
Unit
Min Max
8 Delay from RESET assertion to all pins at reset value3
9 Required RESET duration4
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Power on, internal oscillator
• During STOP, XTAL disabled (PCTL Bit 16 = 0)
• During STOP, XTAL enabled (PCTL Bit 16 = 1)
• During normal operation
10 Delay from asynchronous RESET deassertion to first external address
output (internal reset deassertion)5
• Minimum
• Maximum
13 Mode select set-up time
—
Minimum:
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
2.5 × TC
3.25 × TC + 2.0
20.25 × TC + 10
—
26.0
ns
333.3
—
ns
6.67
—
µs
0.50
—
ms
0.50
—
ms
16.7
—
ns
16.7
—
ns
23.7
—
ns
—
145.0
ns
30.0
—
ns
14 Mode select hold time
0.0
—
ns
15 Minimum edge-triggered interrupt request assertion width
6.6
—
ns
16 Minimum edge-triggered interrupt request deassertion width
6.6
—
ns
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-
purpose transfer output valid caused by first interrupt instruction
execution
Minimum:
4.25 × TC + 2.0
7.25 × TC + 2.0
Minimum:
10 × TC + 5.0
30.4
—
ns
51.0
—
ns
72.0
—
ns
19 Delay from address output valid caused by first interrupt instruction
Maximum:
execute to interrupt request deassertion for level sensitive fast
interrupts1, 7, 8
(WS + 3.75) × TC – 10.94
—
Note 8 ns
20 Delay from RD assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
21 Delay from WR assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
• DRAM for all WS
• SRAM WS = 1
• SRAM WS = 2, 3
• SRAM WS ≥ 4
24 Duration for IRQA assertion to recover from Stop state
Maximum:
(WS + 3.25) × TC – 10.94
—
Note 8 ns
Maximum:
(WS + 3.5) × TC – 10.94
(WS + 3.5) × TC – 10.94
(WS + 3) × TC – 10.94
(WS + 2.5) × TC – 10.94
—
Note 8 ns
—
Note 8 ns
—
Note 8 ns
—
Note 8 ns
5.9
—
ns
25 Delay from IRQA assertion to fetch of first instruction (when exiting
Stop)2, 3
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is PLC × ETC × PDF + (128 K − 1.3
enabled
PLC/2) × TC
(Operating Mode Register Bit 6 = 0)
9.1
ms
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is PLC × ETC × PDF + (23.75 ± 232.5 ns 12.3 ms
not enabled (Operating Mode Register Bit 6 = 1)
0.5) × TC
• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop
(8.25 ± 0.5) × TC
51.7
58.3
ns
Delay)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-7
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