DS2152 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2152

Enhanced T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

PIN

SYMBOL

TYPE

DESCRIPTION

94

RSIG

O Receive Signaling Output

95

RSER

O Receive Serial Data

96

RMSYNC

O Receive Multiframe Sync

97

RFSYNC

O Receive Frame Sync

98

RSYNC

I/O Receive Sync

99

RLOS/LOTC

O Receive Loss Of Sync / Loss of Transmit Clock

100

RSYSCLK

I Receive System Clock

NOTE:

Leave all no connect (NC) pins open circuited.

DS2152

DS2152 PIN DESCRIPTION Table 1-2

TRANSMIT SIDE DIGITAL PINS

Transmit Clock [TCLK]. A 1.544 MHz primary clock. Used to clock data through the transmit side

formatter.

Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when

the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit

side elastic store is enabled.

Transmit Channel Clock [TCHCLK]. A 192 kHz clock which pulses high during the LSB of each

channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with

TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of

channel data.

Transmit Channel Block [TCHBLK]. A user-programmable output that can be forced high or low

during any of the 24 T1 channels. Synchronous with TCLK when the transmit side elastic store is

disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for

blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used

such as Fractional T1, 384 kbps (H0), 768 kbps or ISDN-PRI. Also useful for locating individual

channels in drop-and-insert applications, for external per-channel loopback, and for per-channel

conditioning. See Section 9 for details.

Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit

side elastic store function is enabled. Should be tied low in applications that do not use the transmit side

elastic store. Can be burst at rates up to 8.192 MHz.

Transmit Link Clock [TLCLK]. 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See

Section 11 for details. Transmit Link Data [TLINK].

Transmit Link Data [TLINK]. If enabled via TCR1.2, this pin will be sampled on the falling edge of

TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4) or the Z-bit position

(ZBTSI). See Section 11 for details.

Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the

transmit side. Via TCR2.2, the DS2152 can be programmed to output either a frame or multiframe pulse

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