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DS2152

Enhanced T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2152

1.0 INTRODUCTION

The DS2152 is a superset version of the popular DS2151 T1 Single-Chip Transceiver offering the new

features listed below. All of the original features of the DS2151 have been retained and software created

for the original devices is transferable into the DS2152.

New Features

§ option for non-multiplexed bus operation

§ crystal-less jitter attenuation

§ additional hardware signaling capability including:

– receive signaling reinsertion to a backplane multiframe sync

– availability of signaling in a separate PCM data stream

– signaling freezing

– interrupt generated on change of signaling data

§ per-channel code insertion in both transmit and receive paths

§ full HDLC controller for the FDL with 16-byte buffers in both transmit and receive paths

§ RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

§ 8.192 MHz clock synthesizer

§ per-channel loopback

§ addition of hardware pins to indicate carrier loss & signaling freeze

§ line interface function can be completely decoupled from the framer/formatter to allow:

– interface to optical, HDSL, and other NRZ interfaces

– ability to “tap” the transmit and receive bipolar data streams for monitoring purposes

– ability to corrupt data and insert framing errors, CRC errors, etc.

§ transmit and receive elastic stores now have independent backplane clocks

§ ability to monitor one DS0 channel in both the transmit and receive paths

§ access to the data streams in between the framer/formatter and the elastic stores

§ AIS generation in the line interface that is independent of loopbacks

§ ability to calculate and check CRC6 according to the Japanese standard

§ ability to pass the F-bit position through the elastic stores in the 2.048 MHz backplane mode

§ programmable in-band loop code generator and detector

Functional Description

The analog AMI/B8ZS waveform off the T1 line is transformer-coupled into the RRING and RTIP pins

of the DS2152. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the

framing/multi-frame pattern. The DS2152 contains an active filter that reconstructs the analog received

signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of 0

dB to -36 dB, which allows the device to operate on cables up to 6000 feet in length. The receive side

framer locates D4 (SLC-96) or ESF multiframe boundaries as well as detects incoming alarms, including

carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store

can be enabled in order to absorb the phase and frequency differences between the recovered T1 data

stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock

applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK

can be a bursty clock with speeds up to 8.192 MHz.

The transmit side of the DS2152 is totally independent from the receive side in both the clock

requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic

store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for

T1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter

attenuation mux to the waveshaping and line driver functions. The DS2152 will drive the T1 line from the

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