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DS2152

Enhanced T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2152

Receive Channel Block [RCHBLK]. A user-programmable output that can be forced high or low during

any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic store is disabled.

Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to

a serial UART or LAPD controller in applications where not all T1 channels are used, such as Fractional

T1, 384 kbps service, 768 kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-

insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 9 for

details.

Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the

receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side

elastic store is enabled.

Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either

frame (RCR2.4=0) or multiframe (RCR2.4=1) boundaries. If set to output frame boundaries then via

RCR2.5, RSYNC can also be set to output double-wide pulses on signaling frames. If the receive side

elastic store is enabled via CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a

frame or multiframe boundary pulse is applied. See Section 15 for details.

Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse 1 RCLK wide is output at this pin which

identifies frame boundaries.

Receive Multiframe Sync [RMSYNC]. Only used when the receive side elastic store is enabled. An

extracted pulse, 1 RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If the

receive side elastic store is disabled, then this output will output multiframe boundaries associated with

RCLK.

Receive Data [RDATA]. Updated on the rising edge of RCLK with the data out of the receive side

framer.

Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store

function is enabled. Should be tied low in applications that do not use the elastic store. Can be burst at

rates up to 8.192 MHz.

Receive Signaling Output [RSIG]. Outputs signaling bits in a PCM format. Updated on rising edges of

RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the

receive side elastic store is enabled.

Receive Loss of Sync / Loss of Transmit Clock [RLOS/LOTC]. A dual function output that is

controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high when the

synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been

toggled for 5 µs.

Receive Carrier Loss [RCL]. Set high when the line interface detects a loss of carrier.

Receive Signaling Freeze [RSIGF]. Set high when the signaling data is frozen via either automatic or

manual intervention. Used to alert downstream equipment of the condition.

8 MHz Clock [8MCLK]. A 8.192 MHz output clock that is referenced to the clock that is output at the

RCLK pin and is used to clock data through the receive side framer.

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