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DS1205S

MultiKey Chip

Dallas Semiconductor -> Maxim Integrated 

DS1205S

4. The bus master writes a 0. This deselects ROM2

and ROM3 for the remainder of this search pass,

leaving only ROM1 and ROM4 connected to the

1-wire bus.

5. The bus master performs two more reads and re-

ceives a 0 bit followed by a 1 bit. This indicates that

all devices still coupled to the bus have 0’s as their

second ROM data bit.

6. The bus master then writes a 0 to keep both ROM1

and ROM4 coupled.

7. The bus master executes two reads and receives

two 0 bits. This indicates that both 1 bits and 0 bits

exist as the third bit of the ROM data of the attached

devices.

8. The bus master writes a 0 bit. This deselects ROM1

leaving ROM4 as the only device still connected.

9. The bus master reads the remainder of the ROM bits

for ROM4 and continues to access the part if de-

sired. This completes the first pass and uniquely

identifies one part on the 1-wire bus.

At this point, the bus master repeats the process de-

scribed above to determine the address of the remain-

ing devices on the 1-wire bus by repeating steps 1

though 7.

Note the following:

The bus master learns the unique ID number (ROM data

pattern) of one 1-wire device on each ROM Search op-

eration. The time required to derive the part’s unique ID

is:

960 µS + 3(8+64) X 0.06mS = 13.92mS

The bus master is therefore capable of identifying 60 dif-

ferent 1-wire devices per second.

Additionally, the data obtained from the two reads of

each set of three have the following interpretations:

00 - There are still devices attached which have

conflicting bits in this position.

01 - All devices still coupled have a zero bit in this bit

position.

10 - All devices still coupled have a one bit in this bit

position.

11 - There are no devices attached to the 1-wire

bus.

Transmitting/Receiving Data - All communications on

the 1-wire bus begin with the reset and presence detect

sequence. This sequence ensures the DS1205S is in

the listening mode. The bus master must then transmit

the 1-wire command to the DS1205S. To transmit the

first bit of the 1-wire I/O command, the master pulls the

bus low for 1 µS. This low-going edge informs the

DS1205S that the first bit is being sent. After 1 µS, the

master does one of two things:

1. holds the line low for an additional 70 µS to output a

0 (write a 0) or,

2. lets the bus go high for an additional 70 µS (write a 1).

The state of the bus during this 70 µS time phase deter-

mines the value of the bit. The DS1205S will sense any

rising edge during this 70 µS time phase as a one. After

the 70 µS has lapsed, the bus master must then drive

the bus high for 1 µS. This is the frame sync mentioned

earlier. This process is repeated until all the eight bits

are transmitted. Refer to the timing diagram in Figure

18.

The bus master now reads the family code identifier, fol-

lowed by the data and a CRC. The read cycle is similar

to the write cycle. It is started with the bus master pulling

the bus low for 1 µS. This informs the DS1205S that it

should have data on the bus no later than the 1 µS from

the falling edge. After the 1 µS, the bus master lets go of

the bus and the DS1205S drives the bus. The slave

must hold the data on the bus for an additional 14 µS

minimum (59 µS maximum). During the DS1205S hold-

ing time, the bus master reads the state of the bus. Ideal-

ly, the bus master should read data from the bus 15 µs

after the falling edge. The entire cycle time for one bit

lasts a minimum of 70 µS (140 µS maximum) from the

falling edge. At the end of the cycle, the bus master

drives the bus high for 1 µS. Again, this is like a frame

sync for the next bit. This read sequence is repeated un-

til all the data has been read. See the timing diagram in

Figure 19 for details. If for any reason the transaction

needs to be terminated before all the data is read, the

DS1205S must be reset.

CRC Generation - To validate the transmitted data from

the DS1205S, the bus master must generate a CRC val-

ue for the data as it is received. This generated value is

compared to the value stored in the last eight bits of the

DS1205S. The bus master computes the CRC over the

8-bit family code and all 48 ID number data bits, but NOT

over the stored CRC value itself. The CRC is calculated

using the following polynomial.

CRC = px3 + px2 + 1

If the two CRC values match, the transmission is error-

free.

021798 12/17

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