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CYRF69303

Programmable Radio-on-Chip LPstar

Cypress Semiconductor 

CYRF69303

Clocks

A 12 MHz crystal (30 ppm or better) is directly connected

between XTAL and GND without the need for external

capacitors. A digital clock out function is provided, with

selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This

output may be used to clock an external microcontroller (MCU)

or ASIC. This output is enabled by default, but may be disabled.

The requirements for the crystal to be directly connected to XTAL

pin and GND are:

■ Nominal Frequency: 12 MHz

■ Operating Mode: Fundamental Mode

■ Resonance Mode: Parallel Resonant

■ Frequency Initial Stability: ±30 ppm

■ Series Resistance: <60 ohms

■ Load Capacitance: 10 pF

■ Drive Level: l00 W

The MCU function features an internal oscillator. The clock

generator provides the 12 MHz and 24 MHz clocks that remain

internal to the microcontroller.

GPIO Interface

The MCU function features up to 15 general-purpose I/O (GPIO)

pins.The I/O pins are grouped into three ports (Port 0 to 2). The

pins on Port 0 and Port 1 may each be configured individually

while the pins on Port 2 may only be configured as a group. Each

GPIO port supports high-impedance inputs, configurable pull-up,

open drain output, CMOS/TTL inputs, and CMOS output with up

to two pins that support programmable drive strength of up to

50 mA sink current. Additionally, each I/O pin can be used to

generate a GPIO interrupt to the microcontroller. Each GPIO port

has its own GPIO interrupt vector with the exception of GPIO

Port 0. GPIO Port 0 has three dedicated pins that have

independent interrupt vectors (P0.1, P0.3–P0.4).

Power-on Reset

The power-on reset (POR) circuit detects logic when power is

applied to the device, resets the logic to a known state, and

begins executing instructions at Flash address 0x0000. When

power falls below a programmable trip voltage, it generates reset

or may be configured to generate interrupt.

Timers

The free-running 16-bit timer provides two interrupt sources: the

programmable interval timer with 1 s resolution and the

1.024 ms outputs. The timer can be used to measure the

duration of an event under firmware control by reading the timer

at the start and at the end of an event, then calculating the

difference between the two values.

Power Management

The operating voltage of the device is 2.7 V to 3.6 V DC, which

is applied to VCC and VBAT pins. The device can be shut down

to a fully static sleep mode by writing to the FRC END = 1 and

END STATE = 000 bits in the XACT_CFG_ADR register over the

SPI interface. The device enters sleep mode within 35 µs after

the last SCK positive edge at the end of this SPI transaction.

Alternatively, the device may be configured to automatically

enter sleep mode after completing the packet transmission or

reception. When in sleep mode, the on-chip oscillator is stopped,

but the SPI interface remains functional. The device wakes from

sleep mode automatically when the device is commanded to

enter transmit or receive mode. When resuming from sleep

mode, there is a short delay while the oscillator restarts. The

device can be configured to assert the IRQ pin when the

oscillator has stabilized.

The following Figure 3 is an example of the circuit used when the

supply voltage is always above 2.7 V. This could be three 1.5 V

battery cells in series along with a linear regulator, or some

similar power source. Figure 4 on page 9 shows an example of

using an external boost to supply power to the device.

Figure 3. Example Circuit - Linear Regulator

VCC

0.047µF

0.047µF

0.047µF

0.047µF

0.047µF

0.047µF

0.047µF

0.047µF

Vcc

VDD_MICRO

0.1µF

CYRF69303

Document Number: 001-66502 Rev. *D

Page 8 of 70

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