STK14C88-3N45I Ver la hoja de datos (PDF) - Simtek Corporation
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STK14C88-3N45I Datasheet PDF : 13 Pages
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STK14C88-3
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V-3.6V)e
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK14C88-3-35 STK14C88-3-45
MIN MAX MIN MAX
12
tAVAV
13
tWLWH
14
tELWH
15
tDVWH
16
tWHDX
17
tAVWH
18
tAVWL
19
tWHAX
20
tWLQZi, j
21
tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
tWP Write Pulse Width
tCW Chip Enable to End of Write
tDW Data Set-up to End of Write
tDH Data Hold after End of Write
tAW Address Set-up to End of Write
tAS Address Set-up to Start of Write
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
tOW Output Active after End of Write
35
45
25
30
25
30
12
15
0
0
25
30
0
0
0
0
13
15
5
5
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
ADDRESS
12
tAVAV
14
tELWH
E
19
tWHAX
STK14C88-3-55
MIN
MAX
55
40
40
25
0
40
0
0
20
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W
DATA IN
DATA OUT
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
16
tWHDX
21
tWHQX
SRAM WRITE CYCLE #2: E Controlledk, l
ADDRESS
12
tAVAV
18
tAVEL
14
tELEH
19
tEHAX
E
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
November 2003
4 Document Control # ML0015 rev 0.3
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