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CY7C421-20JXI

512 × 9 Asynchronous FIFO

Cypress Semiconductor 

CY7C421

Use of the Empty and Full Flags

To achieve maximum frequency, the flags must be valid at the

beginning of the next cycle. However, because they can be

updated by either edge of the read or write signal, they must be

valid by one-half of a cycle. Cypress FIFOs meet this

requirement.

The reason for why the flags should be valid by the next cycle is

complex. The “effective pulse width violation” phenomenon can

occur at the full and empty boundary conditions, if the flags are

not properly used. The empty flag must be used to prevent

reading from an empty FIFO and the full flag must be used to

prevent writing into a full FIFO.

For example, consider an empty FIFO that is receiving read

pulses. Because the FIFO is empty, the read pulses are ignored

by the FIFO, and nothing happens. Next, a single word is written

into the FIFO, with a signal that is asynchronous to the read

signal. The (internal) state machine in the FIFO goes from empty

to empty+1. However, it does this asynchronously with respect

to the read signal, so that the effective pulse width of the read

signal cannot be determined, because the state machine does

not look at the read signal until it goes to the empty+1 state.

Similarly, the minimum write pulse width may be violated by

trying to write into a full FIFO, and asynchronously performing a

read. The empty and full flags are used to avoid these effective

pulse width violations, but to do this and operate at the maximum

frequency, the flag must be valid at the beginning of the next

cycle.

Figure 14. Depth Expansion

W

9

D

FULL

MR

XO

FF

EF

9

CY7C421

FL

XI

XO

FF

EF

9

CY7C421

FL

XI

XO

*

FF

EF

9

CY7C421

FL

XI

* FIRST DEVICE

R

9

Q

VCC

EMPTY

Document Number: 38-06001 Rev. *H

Page 14 of 21

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