CY7C1359A-100AC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1359A-100AC Datasheet PDF : 24 Pages
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CY7C1359A/GVT71256T18
Truth Table[5, 6, 7, 8, 9, 10, 11]
Operation
Address
Used CE CE2 CE2 ADSP ADSC ADV WRITE OE
Deselected Cycle, Power Down None H X X
X
L
X
X
X
Deselected Cycle, Power Down None L X L
L
X
X
X
X
Deselected Cycle, Power Down None L H X
L
X
X
X
X
Deselected Cycle, Power Down None L X L
H
L
X
X
X
Deselected Cycle, Power Down None L H X
H
L
X
X
X
READ Cycle, Begin Burst
External L L H
L
X
X
X
L
READ Cycle, Begin Burst
External L L H
L
X
X
X
H
WRITE Cycle, Begin Burst
External L L H
H
L
X
L
X
READ Cycle, Begin Burst
External L L H
H
L
X
H
L
READ Cycle, Begin Burst
External L L H
H
L
X
H
H
READ Cycle, Continue Burst
Next
XX X
H
H
L
H
L
READ Cycle, Continue Burst
Next
XX X
H
H
L
H
H
READ Cycle, Continue Burst
Next H X X
X
H
L
H
L
READ Cycle, Continue Burst
Next H X X
X
H
L
H
H
WRITE Cycle, Continue Burst
Next X X X
H
H
L
L
X
WRITE Cycle, Continue Burst
Next H X X
X
H
L
L
X
READ Cycle, Suspend Burst
Current X X X
H
H
H
H
L
READ Cycle, Suspend Burst
Current X X X
H
H
H
H
H
READ Cycle, Suspend Burst
Current H X X
X
H
H
H
L
READ Cycle, Suspend Burst
Current H X X
X
H
H
H
H
WRITE Cycle, Suspend Burst Current X X X
H
H
H
L
X
WRITE Cycle, Suspend Burst Current H X X
X
H
H
L
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Partial Truth Table for READ/WRITE[12]
Function
GW
BWE
WEH
WEL
READ
H
H
X
X
READ
H
L
H
H
WRITE one byte
H
L
L
H
WRITE all bytes
H
L
L
L
WRITE all bytes
L
X
X
X
Notes:
7. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH. It is assumed in this truth table that DEN is LOW.
8. WEL enables write to DQ1–DQ9. WEH enables write to DQ10–DQ18.
9. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
10. Suspending burst generates wait cycle.
11. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
12. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP is HIGH along with DEN being LOW.
Document #: 38-05120 Rev. **
Page 6 of 24
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