CY7C1340G Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C1340G

4-Mbit (128K x 32) Pipelined DCD Sync SRAM

Cypress Semiconductor 

CY7C1340G

Document History Page

Document Title: CY7C1340G 4-Mb (128K x 32) Pipelined DCD Sync SRAM

Document Number: 38-05522

Orig. of

REV. ECN NO. Issue Date Change

Description of Change

**

224370 See ECN RKF New Data Sheet

*A 288909 See ECN VBL In Ordering Info Section, change TQFP to PB-Free TQFP

*B 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP Package as per

JEDEC standards and updated the Pin Definitions accordingly

Modified VOL, VOH test conditions

Removed 200Mhz Speed Bin

Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal Resis-

tance table

Updated the Ordering Information by shading and unshading MPNs as per

availability

*C 419256 See ECN RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

North First Street” to “198 Champion Court”

Modified test condition from VIH < VDD to VIH < VDD

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the Ordering Infor-

mation table

Replaced Package Diagram of 51-85050 from *A to *B

Updated the Ordering Information

*D 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Updated the Ordering Information table.

Document #: 38-05522 Rev. *D

Page 16 of 16

Share Link: