SA7026DK Ver la hoja de datos (PDF) - Philips Electronics
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SA7026DK Datasheet PDF : 14 Pages
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Philips Semiconductors
1.3GHz low voltage fractional-N dual synthesizer
Objective specification
SA7026
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 address bits. Figure 8 shows the
timing diagram of the serial input. When the STROBE goes active
HIGH, the clock is disabled and the data in the shift register remains
unchanged. Depending on the 2 address bits the data is latched into
Serial bus timing characteristics. See Figure 8.
VDD = VDDCP =+3.0V; Tamb = +25°C unless otherwise specified.
SYMBOL
PARAMETER
Serial programming clock; CLK
tr
Input rise time
tf
Input fall time
Tcy
Clock period
Enable programming; STROBE
tSTART
tW
TSU;E
Delay to rising clock edge
Minimum inactive pulse width
Enable set-up time to next clock edge
Register serial input data; DATA
tSU;DAT
tHD;DAT
Input data to clock set-up time
Input data to clock hold time
different working registers or temporary registers. In order to fully
program the synthesizer, 3 words must be sent: C, B, and A. Table 1
shows the format and the contents of each word. The D word is for
testing purposes only. The data for the fractional compensation
DAC, FC is stored by the B word in temporary registers. When the A
word is loaded, the data of these temporary registers is loaded
together with the main divider ratio.
MIN.
TYP.
MAX.
UNIT
–
10
40
ns
–
10
40
ns
100
–
–
ns
40
–
–
ns
1/fcomp
–
–
ns
20
–
–
ns
20
–
–
ns
20
–
–
ns
Application information
tSU;DAT
Tcy
tHD;DAT
tr
tf
tSU;E
CLK
DATA
MSB
LSB
ADDRESS
STROBE
tSTART
Figure 8. Serial Bus Timing Diagram
tw
SR01417
1998 Oct 13
11
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