CY7C1212F Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C1212F

1-Mbit (64K x 18) Pipelined Sync SRAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read/Write Cycle Timing[17, 19, 20]

tCYC

CLK

ADSP

tCH tCL

tADS tADH

ADSC

ADDRESS A1

tAS tAH

A2

BWE,

BW[A:B]

CE

tCES tCEH

A3

A4

tWES tWEH

CY7C1212F

A5

A6

ADV

OE

tCO

tDS tDH

tOELZ

Data In (D)

High-Z

D(A3)

tCLZ

tOEHZ

Data Out (Q)

High-Z

Q(A1)

Q(A2)

Back-to-Back READs

Single WRITE

Q(A4)

Q(A4+1) Q(A4+2)

BURST READ

Q(A4+3)

DON’T CARE

UNDEFINED

Notes:

19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

20. GW is HIGH.

D(A5)

D(A6)

Back-to-Back

WRITEs

Document #: 38-05423 Rev. *A

Page 12 of 15

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