CY7C1061AV25 Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C1061AV25 Datasheet PDF : 11 Pages
| |||
PRELIMINARY
CY7C1061AV25
AC Test Loads and Waveforms[3]
OUTPUT
Z0 = 50Ω
50Ω
30 pF*
VTH = VDD/2
(a) * Capacitive Load consists of all com-
ponents of the test environment.
2.5V
R1 1667 Ω
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE (b)
R2
1538Ω
2.5V
GND
Rise time > 1V/ns
ALL INPUT PULSES
90%
10%
(c)
90%
10%
Fall time:
> 1V/ns
AC Switching Characteristics Over the Operating Range [4]
-8
-10
-12
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tpower
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[8, 9]
VCC(typical) to the first access[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z[6]
CE1 LOW/CE2 HIGH to Low-Z[6]
CE1 HIGH/CE2 LOW to High-Z[6]
CE1 LOW/CE2 HIGH to Power-up[7]
CE1 HIGH/CE2 LOW to Power-down[7]
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
1
1
1
ms
8
10
12
ns
8
10
12
ns
3
3
3
ns
8
10
12
ns
5
5
6
ns
1
1
1
ns
5
5
6
ns
3
3
3
ns
5
5
6
ns
0
0
0
ns
8
10
12
ns
5
5
6
ns
1
1
1
ns
5
5
6
ns
tWC
Write Cycle Time
8
10
12
ns
tSCE
CE1 LOW / CE2 HIGH to Write End
6
7
8
ns
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.5V, and output loading of the specified
IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5. This part has a voltage regulator which steps down the voltage from 2.5V to 2V internally. tpower time has to be provided initially before a Read/Write operation
is started.
6. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05331 Rev. **
Page 4 of 11
Share Link: 