CY7C1049CV33-15ZE Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY7C1049CV33-15ZE

4-Mbit (512K x 8) Static RAM

Cypress Semiconductor 

CY7C1049CV33

Switching Waveforms

Read Cycle No. 1[12, 13]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled)[13, 14]

ADDRESS

tRC

CE

DATA VALID

OE

DATA OUT

VCC

SUPPLY

CURRENT

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Notes:

6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

7. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.

8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these

signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.

11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

12. Device is continuously selected. OE, CE = VIL.

13. WE is HIGH for Read cycle.

Document #: 38-05006 Rev. *C

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