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A386DX Datasheet PDF : 139 Pages
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Intel386TM DX MICROPROCESSOR
SYSTEM ADDRESS REGISTERS
47 32-BIT LINEAR BASE ADDRESS 16 15 LIMIT 0
GDTR
IDTR
SYSTEM SEGMENT
REGISTERS
V
W
15
0
TR
SELECTOR
LDTR
SELECTOR
DESCRIPTOR REGISTERS (AUTOMATICALLY LOADED)
V
W
32-BIT LINEAR BASE ADDRESS 32-BIT SEGMENT LIMIT ATTRIBUTES
Figure 2-7 System Address and System Segment Registers
LDTR and TR
These registers hold the 16-bit selector for the LDT
descriptor and the TSS descriptor respectively
The LDT and TSS segments since they are task-
specific segments are defined by selector values
stored in the system segment registers Note that a
segment descriptor register (programmer-invisible)
is associated with each system segment register
Test Registers Two registers are used to control
the testing of the RAM CAM (Content Addressable
Memories) in the Translation Lookaside Buffer por-
tion of the Intel386 DX TR6 is the command test
register and TR7 is the data register which contains
the data of the Translation Lookaside buffer test
Their use is discussed in section 2 11 Testability
Figure 2-8 shows the Debug and Test registers
2 3 8 Debug and Test Registers
Debug Registers The six programmer accessible
debug registers provide on-chip support for debug-
ging Debug Registers DR0–3 specify the four linear
breakpoints The Debug Control Register DR7 is
used to set the breakpoints and the Debug Status
Register DR6 displays the current state of the
breakpoints The use of the debug registers is de-
scribed in section 2 12 Debugging support
DEBUG REGISTERS
31
0
LINEAR BREAKPOINT ADDRESS 0
LINEAR BREAKPOINT ADDRESS 1
LINEAR BREAKPOINT ADDRESS 2
LINEAR BREAKPOINT ADDRESS 3
Intel reserved Do not define
Intel reserved Do not define
BREAKPOINT STATUS
BREAKPOINT CONTROL
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
TEST REGISTERS (FOR PAGE CACHE)
31
0
TEST CONTROL
TR6
TEST STATUS
TR7
Figure 2-8 Debug and Test Registers
2 3 9 Register Accessibility
There are a few differences regarding the accessibil-
ity of the registers in Real and Protected Mode Ta-
ble 2-1 summarizes these differences See Section
4 Protected Mode Architecture for further details
2 3 10 Compatibility
VERY IMPORTANT NOTE
COMPATIBILITY WITH FUTURE PROCESSORS
In the preceding register descriptions note cer-
tain Intel386 DX register bits are Intel reserved
When reserved bits are called out treat them as
fully undefined This is essential for your soft-
ware compatibility with future processors Fol-
low the guidelines below
1) Do not depend on the states of any unde-
fined bits when testing the values of defined
register bits Mask them out when testing
2) Do not depend on the states of any unde-
fined bits when storing them to memory or
another register
3) Do not depend on the ability to retain infor-
mation written into any undefined bits
4) When loading registers always load the unde-
fined bits as zeros
14
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