CY7B9940V-2AC(2002) Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7B9940V-2AC Datasheet PDF : 9 Pages
| |||
RoboClockII™ Junior
CY7B9930V
CY7B9940V
Divide Matrix
The Divide Matrix is comprised of three independent banks:
two banks of clock outputs and one bank for feedback. Each
clock output bank has two pairs of low-skew, high-fanout
output buffers ([1:2]Q[A:B][0:1]), and an output disable
(DIS[1:2]).
The feedback bank has one pair of low-skew, high-fanout
output buffers (QFA[0:1]). One of these outputs may connect
to the selected feedback input (FBKA+). This feedback bank
also has two divider function selects FBDS[0:1].
The divide capabilities for each bank are shown in Table 2.
Table 2. Output Divider Function
Function
Selects
FBDS1
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
FBDS0
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
Output Divider Function
Bank1
Feedback
Bank2
Bank
/1
/1
/1
/1
/1
/2
/1
/1
/3
/1
/1
/4
/1
/1
/5
/1
/1
/6
/1
/1
/8
/1
/1
/10
/1
/1
/12
Output Disable Description
The outputs of Bank 1 and Bank 2 can be independently put
into a HOLD-OFF or high-impedance state. The combination
of the Output_Mode and DIS[1:2] inputs determines the clock
outputs’ state for each bank. When the DIS[1:2] is LOW, the
outputs of the corresponding bank will be enabled. When the
DIS[1:2] is HIGH, the outputs for that bank will be disabled to
a high-impedance (HI-Z) or HOLD-OFF state depending on
the Output_Mode input. Table 3 defines the disabled output
functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input (DIS[1:2]) is HIGH. When disabled to the
HOLD-OFF state, outputs are driven to a logic LOW state on
its falling edge. This ensures the output clocks are stopped
without glitch. When a bank of outputs is disabled to HI-Z state,
the respective bank of outputs will go HI-Z immediately.
Table 3. DIS[1:2] Pin Functionality
OUTPUT_MODE
HIGH/LOW
HIGH
LOW
MID
DIS[1:2]/FBDIS
LOW
HIGH
HIGH
X
Output Mode
ENABLED
HI-Z
HOLD-OFF
FACTORY TEST
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit (tPD).
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output will
be forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output
to indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH,
a “Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW.
This time out period is based upon a divided down reference
clock.
This assumes that there is activity on the selected REF input.
If there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal
PLL.
Factory Test Mode Description
The device will enter factory test mode when the
OUTPUT_MODE is driven to MID. In factory test mode, the
device will operate with its internal PLL disconnected; input
level supplied to the reference input will be used in place of the
PLL output. In TEST mode the selected FB input must be tied
LOW. All functions of the device are still operational in factory
test mode except the internal PLL and output bank disables.
The OUTPUT_MODE input is designed to be a static input.
Dynamically toggling this input from LOW to HIGH may tempo-
rarily cause the device to go into factory test mode (when
passing through the MID state).
Factory Test Reset
When in factory test mode (OUTPUT_MODE = MID), the
device can be reset to a deterministic state by driving the DIS2
input HIGH. When the DIS2 input is driven HIGH in factory test
mode, all clock outputs will go to HI-Z; after the selected
reference clock pin has 5 positive transitions, all the internal
finite state machines (FSM) will be set to a deterministic state.
The deterministic state of the state machines will depend on
the configurations of the divide selects and frequency select
input. All clock outputs will stay in high-impedance mode and
all FSMs will stay in the deterministic state until DIS2 is
deasserted. When DIS2 is deasserted (with OUTPUT_MODE
still at MID), the device will re-enter factory test mode.
Document #: 38-07271 Rev. *B
Page 3 of 9
[+] Feedback
Share Link: 