CY7B9940V-2AC(2002) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7B9940V-2AC
(Rev.:2002)

High-Speed Multi-Frequency PLL Clock Buffer

Cypress Semiconductor 

RoboClockII™ Junior

CY7B9930V

CY7B9940V

Pin Definitions[1]

Name

I/O Type

Description

FBKA

Input LVTTL Feedback Input.

REFA+, REFA– Input LVTTL/ Reference Inputs: These inputs can operate as differential PECL or single-ended TTL

REFB+, REFB–

LVDIFF reference inputs to the PLL. When operating as a single-ended LVTTL input, the comple-

mentary input must be left open.

REFSEL

Input LVTTL

Reference Select Input: The REFSEL input controls how the reference input is configured.

When LOW, it will use the REFA pair as the reference input. When HIGH, it will use the

REFB pair as the reference input. This input has an internal pull-down.

FS

Input 3-level Frequency Select: This input must be set according to the nominal frequency (fNOM). See

Input Table 1.

FBDS[0:1]

Input 3-level Feedback Divider Function Select. These inputs determine the function of the QFA0 and

Input QFA1 outputs. See Table 2.

DIS[1:2]

Input LVTTL

Output Disable: Each input controls the state of the respective output bank. When HIGH,

the output bank is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is deter-

mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See Table 3.

These inputs each have an internal pull-down.

LOCK

Output LVTTL PLL Lock Indicator: When HIGH, this output indicates the internal PLL is locked to the

reference signal. When LOW, the PLL is attempting to acquire lock.

Output_Mode

Input

3-Level

Input

Output Mode: This pin determines the clock outputs’ disable state. When this input is HIGH,

the clock outputs will disable to high-impedance (HI-Z). When this input is LOW, the clock

outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter factory test

mode.

QFA[0:1]

Output LVTTL

Clock Feedback Output: This pair of clock outputs is intended to be connected to the FB

input. These outputs have numerous divide options. The function is determined by the

setting of the FBDS[0:1] pins.

[1:2]Q[A:B][0:1] Output LVTTL Clock Output.

VCCN

PWR Output Buffer Power: Power supply for each output pair.

VCCQ

PWR Internal Power: Power supply for the internal circuitry.

GND

PWR Device Ground.

Block Diagram Description

VCO, Control Logic, and Divide Generator

Phase Frequency Detector and Filter

The VCO accepts analog control inputs from the PLL filter

These two blocks accept signals from the REF inputs (REFA+,

REFA–, REFB+ or REFB–) and the FB input (FBKA).

Correction information is then generated to control the

frequency of the Voltage Controlled Oscillator (VCO). These

two blocks, along with the VCO, form a Phase-Locked Loop

(PLL) that tracks the incoming REF signal.

The RoboClockII Junior has a flexible REF input scheme.

These inputs allow the use of either differential LVPECL or

single-ended LVTTL inputs. To configure as single-ended

LVTTL inputs, the complementary pin must be left open (inter-

block. The FS control pin setting determines the nominal

operational frequency range of the divide by one output (fNOM)

of the device. fNOM is directly related to the VCO frequency.

There are two versions of the RoboClockII Junior, a low-speed

device (CY7B9930V) where fNOM ranges from 12 MHz to 100

MHz, and a high-speed device (CY7B9940V) which ranges

from 24 MHz to 200 MHz. The FS setting for each device is

shown in Table 1. The fNOM frequency is seen on

“divide-by-one” outputs.

Table 1. Frequency Range Select

nally pulled to 1.5V), then the other input pin can be used as

CY7B9930V

CY7B9940V

a LVTTL input. The REF inputs are also tolerant to hot

insertion.

The REF inputs can be changed dynamically. When changing

from one reference input to the other reference input of the

FS[2]

LOW

fNOM (MHz)

Min.

Max.

12

26

fNOM (MHz)

Min.

Max.

24

52

same frequency, the PLL is optimized to ensure that the clock MID

24

52

48

100

outputs period will not be less than the calculated system

budget (tMIN = tREF (nominal reference clock period) – tCCJ

HIGH

48

100

96

200[3]

(cycle-to-cycle jitter) – tPDEV (max. period deviation)) while

reacquiring lock.

Note:

1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination

circuitry holds an unconnected input to VCC/2.

2. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO. fNOM always appears on an output when the output is operating

in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.

3. The maximum output frequency is 200 MHz.

Document #: 38-07271 Rev. *B

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