DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

CY14B101P(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza
componentes Descripción
Fabricante
CY14B101P Datasheet PDF : 35 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
PRELIMINARY
CY14B101P
Table 10. Register Map Detail (continued)
Register
Description
Watchdog Timer
0x07
WDS
WDW
WDT
0x06
WIE
AIE
PFE
0
H/L
P/L
D7
D6
D5
D4
D3
D2
D1
D0
WDS
WDW
WDT
Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect. The
bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.
Watchdog write enable. Setting this bit to ‘1’ disables any WRITE to the watchdog timeout value (D5–D0). This enables
the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to ‘0’ allows bits D5–D0 to
be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in
Watchdog Timer on page 16.
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a
multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting
of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was
set to 0 on a previous cycle.
Interrupt Status/Control
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
0
H/L
P/L
0
0
Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT pin and
the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag.
Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the alarm
match only affects the AF flag.
Power fail enable. When set to ‘1’, the alarm match drives the INT pin and the PF flag. When set to ‘0’, the power fail
monitor affects only the PF flag.
Reserved for future use
HIGH/LOW. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0’, the INT pin is open drain, active LOW.
Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L) until the flags register is read.
0x05
M
0x04
Alarm - Day
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s alarm date
Alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit
to ignore the date value.
Alarm - Hours
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s alarm hours
Alarm hours
M
0x03
M
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the hours value.
Alarm - Minutes
D7
D6
D5
D4
D3
D2
D1
D0
M
10s alarm minutes
Alarm minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the match
circuit to ignore the minutes value.
Document #: 001-61932 Rev. *B
Page 21 of 35

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]