CXD3011R-1 Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD3011R-1

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony Semiconductor 

CXD3011R-1

Pin Symbol

I/O

No.

Description

119 LOCK

I/O 1, 0

GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.

If GFS is low eight consecutive samples, this pin outputs low. Input when

LKIN = high. (See $3E.)

120 SSTP

I

Disc innermost track detection signal input.

121 DVSS5

Digital GND.

122 DTS0

I

Test pin. Normally fixed to low.

123 TES2

I

Test pin. Normally fixed to low.

124 TES3

I

Test pin. Normally fixed to low.

129 PWMI I

Spindle motor external pin input.

130 DVDD5

Digital power supply.

131 VCOO O 1, 0 Analog EFM PLL oscillation circuit output.

132 VCOI

I

Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.

133 TEST

I

Test pin. Normally fixed to low.

134 PDO

O 1, Z, 0 Analog EFM PLL charge pump output.

135 VCKI

I

Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.

Set VCKI to low when the external clock is not input to this pin.

136 V16M O 1, 0 Wide-band EFM PLL VCO2 oscillation output.

137 AVDD2

Analog power supply.

138 IGEN

I

Connects the operational amplifier current source reference resistance.

139 AVSS2

— Analog GND.

140 ADIO O

Operational amplifier output.

141 RFDC I

RF signal input.

142 CE

I

Center servo analog input.

143 TE

I

Tracking error signal input.

∗In the CXD3011R, the following pins are NC.

Pins 1, 18 to 21, 36, 37, 53 to 56, 72, 73, 89 to 92, 108, 109, 125 to 128 and 144

Notes) • The 64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's complement

output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync

protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the

EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.)

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)

• C2PO represents the data error status.

• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.

–8–

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