CXA3086 Ver la hoja de datos (PDF) - Sony Semiconductor

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CXA3086

6-bit 140MSPS Flash A/D Converter

Sony Semiconductor 

CXA3086Q

Notes on Operation

• The CXA3086Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input.

Characteristic impedance should be properly matched to ensure optimum performance during high-speed

operation.

• The power supply and grounding have a profound influence on converter performance. The power supply

and grounding method are particularly important during high-speed operation. General points for caution are

as follows.

— The ground pattern should be as large as possible. It is recommended to make the power supply and

ground patterns wider at an inner layer using a multi-layer board.

— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the

respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc

and DVcc lines at one point each via a ferrite-bead filter Shorting the AGND and DGND patterns in one

place immediately under the A/D converter improves A/D converter performance.

— Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a

0.1µF or larger ceramic chip capacitor.

(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.)

— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring

capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output

waveform since the original output slew rate is quite fast.

• The analog input pin VIN has an input capacitance of approximately 7pF. To drive the A/D converter with

proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance

or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using

chip parts for resistors and capacitors, etc.

• The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them

to AGND with an approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible.

• The offset for residual resistance is generated each for the reference voltage pins VRT and VRB.

When the offset voltage has no influence on the IC operation, the voltage should be applied to the VRT and

VRB pins directly, keeping the VRBS pin open. When the reference voltage is to be supplied to these pins

precisely, form the feedback loop circuit with VRT and VRB as a force pin and adjust the offset voltage to be

0V. See the “Application Circuit 2” for details.

• If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,

approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as threshold

voltage VBB as it is too weak.

• When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When

the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open.

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