CS61583 Ver la hoja de datos (PDF) - Cirrus Logic
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CS61583 Datasheet PDF : 44 Pages
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CS61583
The first bit (shifted in first) selects between an
output-enabled state (bit set to 1) or high-imped-
ance state (bit set to 0). The second bit shifted in
contains the test data that may be output on the
pin. Therefore, two J-TCK cycles are required to
load test data for each output pin.
BSR bits
0-2
3-5
6
7
8-9
10-11
12-13
14-16
17-19
20
21-23
24-26
27-29
30-32
33-35
36-38
39-41
42-44
45
46-48
49-50
51-52
53-54
55
56
57-59
60-62
63
64
65
66
Pin Name
LOS1
TNEG1/AIS1
TPOS1/TDATA1
TCLK1
RNEG1/BPV1
RPOS1/RDATA1
RCLK1
ATTEN1
RLOOP1
LLOOP1
LLOOP2
TAOS1
TAOS2
CON01
CON02
CON11
CON12
CON21
CON22
AMI1
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
TCLK2
TPOS2/TDATA2
TNEG2/AIS2
LOS2
AMI2
CODER2
RLOOP2
CODER1
Pad Type
bi-directional2
bi-directional
input
input
output
output
output
bi-directional1
bi-directional1
input
bi-directional1
bi-directional1
bi-directional1
bi-directional1
bi-directional1
bi-directional1
bi-directional1
bi-directional1
input
bi-directional1
output
output
output
input
input
bi-directional
bi-directional2
input
input
input
input
1. Configure pad as an input.
2. Configure pad as an output.
Table 5. Boundary Scan Register
16
The bi-directional pins have three bits in the
BSR to define input, output high, output low, or
high impedance. The first bit shifted into the
BSR configures the output driver as high-imped-
ance (bit set to 0) or active (bit set to 1). The
second bit shifted into the BSR sets the output
value when the first bit is 1. The third bit cap-
tures the value of the pin. This pin may have its
value set externally as an input (if the first bit is
0) or set internally as an output (if the first bit is
1). To configure a pad as an input, the J-TDI
pattern is 0X0. To configure a pad as an output,
the J-TDI pattern is 1X1. Therefore, three J-TCK
cycles are required to load test data for each bi-
directional pin.
Device Identification Register: The DIR provides
the manufacturer, part number, and version of the
CS61583. This information can be used to verify
that the proper version or revision number has
been used in the system under test. The DIR is 32
bits long and is partitioned as shown in figure 11.
MSB
LSB
31 28 27
12 11
10
00000000000000000011000011001001
(4 bits)
(16 bits)
(11 bits)
BIT #(s)
31-28
27-12
11-1
0
FUNCTION
Version number
Part Number
Manufacturer Number
Constant Logic ’1’
Total Bits
4
16
11
1
Figure 11. Device Identification Register
Data from the DIR is shifted out to J-TDO LSB
first.
Bypass Register: The Bypass register consists of
a single bit, and provides a serial path between
J-TDI and J-TDO, bypassing the BSR. This al-
lows bypassing specific devices during certain
board-level tests. This also reduces test access
times by reducing the total number of shifts re-
quired from J-TDI to J-TDO.
DS172PP5
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