CS5462 Ver la hoja de datos (PDF) - Cirrus Logic

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CS5462

Low Cost Power/Energy IC with Pulse Output

Cirrus Logic 

CS5462

DIGITAL CHARACTERISTICS (Note 6)

Parameter

Symbol

Min

Typ

High-Level Input Voltage

VIH

XIN

RESET

(VD+) - 0.5 -

0.8 VD+

-

Low-Level Input Voltage (VD = 5 V)

VIL

XIN

RESET

-

-

-

-

Low-Level Input Voltage (VD = 3.3 V)

VIL

XIN

RESET

-

-

-

-

High-Level Output Voltage (except XOUT)

Iout = +5 mA VOH (VD+) - 1.0 -

Low-Level Output Voltage (except XOUT)

Iout = -5 mA VOL

-

-

Input Leakage Current

Iin

-

±1

Digital Output Pin Capacitance

Cout

-

5

Drive Current FOUT, E1, E2, NEG, CPUCLK

90

Max

-

-

1.5

0.2 VD+

0.3

0.2 VD+

-

0.4

±10

-

Unit

V

V

V

V

V

V

V

V

µA

pF

mA

Notes: 6. All measurements performed under static conditions.

SWITCHING CHARACTERISTICS

Parameter

Symbol Min

Typ

Max Unit

Master Clock Frequency

Internal Gate Oscillator MCLK

3

4.096

5

MHz

Master Clock Duty Cycle

40

-

60

%

CPUCLK Duty Cycle

(Note 7)

40

60

%

Rise Times

(Note 8)

Any Digital Input trise

Any Digital Output

-

-

1.0

µs

-

50

-

ns

Fall Times

(Note 8)

Any Digital Input

tfall

Any Digital Output

-

-

1.0

µs

-

50

-

ns

Start-up

Oscillator Start-Up Time

XTAL = 4.096 MHz (Note 9) tost

-

60

-

ms

7. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this

specification.

8. Specified using 10% and 90% points on wave-form of interest. Output loaded wi th 50pF.

9. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

9

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