CDB4955A Ver la hoja de datos (PDF) - Cirrus Logic
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CDB4955A Datasheet PDF : 60 Pages
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CS4954 CS4955
Start of
VSYNC
Field 1
262 263 1
2
3
4
5
6
7
8
9 10
22
Field 2
261 262 1
2
3
4
5
6
7
8
9 10
22
Start of
VSYNC
Field 3
262 263 1
2
3
4
5
6
7
8
9 10
22
Field 4
261 262 1
2
3
4
5
6
7
8
9 10
22
Burst begins with positive half-cycle
Burst phase = reference phase = 180 0relative to B-Y
Burst begins with negative half-cycle
Burst phase = reference phase = 1800relative to B-Y
Figure 9. NTSC Video Non-Interlaced Progressive Scan Timing
5.4 Digital Video Input Modes
The CS4954/5 provides two different digital video
input modes that are selectable through the
IN_MODE bit in the CONTROL_0 Register.
In Mode 0 and upon RESET, the CS4954/5 de-
faults to output a solid color (one of a possible of
256 colors). The background color is selected by
writing the BKG_COLOR Register (0x08). The
colorspace of the register is RGB 3:3:2 and is unaf-
fected by gamma correction. The default color fol-
lowing RESET is blue.
In Mode 1 the CS4954/5 supports a single 8-bit
27 MHz CbYCrY source as input on the V [7:0]
pins. Input video timing can be ITU-R.BT601 mas-
ter or slave or ITU-R.BT656.
5.5 Multi-standard Output Format Modes
The CS4954/5 supports a wide range of output for-
mats compatible with worldwide broadcast stan-
dards. These formats include NTSC-M, NTSC-J,
PAL-B/D/G/H/I, PAL-M, PAL-N, and PAL Com-
bination N (PAL-Nc) which is the broadcast stan-
dard used in Argentina. After RESET, the CS4954/5
defaults to NTSC-M operation with ITU-R.BT601
analog timing. NTSC-J can also be supported in the
Japanese format by turning off the 7.5 IRE pedestal
through the PED bit in the CONTROL_1 Register
(0x01).
Output formats are configured by writing control
registers with the values shown in Table 3.
NOTE 1: The FIELD pin (pin 9) remains an output pin in SLAVE mode. However, the FIELD pin state does not
toggle in SLAVE mode and its output state should be considered random.
DS278F6
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