CP2120 Ver la hoja de datos (PDF) - Silicon Laboratories
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CP2120 Datasheet PDF : 24 Pages
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DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Various small text changes.
Updated 4.1 Pin Out Chart.
Updated 4.2 Pin Out Diagram.
Updated Figure 2. SPI Bus Typical Connections.
Added Table 3. Internal Register Addresses.
Updated all CP2120 command drawings.
Added section 6.1 Determining Pull-Up Register
Values.
Changed appearance of all Internal Register
Definition charts.
Changed contents of Section 8. CP2120 Revision
Number.
Revision 0.2 to Revision 0.3
Removed references to power down mode.
Corrected Equation 1, “I2C Clock Frequency,” on
page 13.
In Internal Register 4, “I2CTO2: Additional I2C Time
Outs,” on page 15, changed Internal Register
Address to “0x09”.
In Internal Register 5, “I2CSTAT: I2C Status
Register,” on page 16, changed all bits to “R” instead
of “R/W”
In Internal Register 6, “RXBUFF: Receive Buffer
Size Register,” on page 17, changed all bits to “R”
instead of “R/W”.
Revision 0.3 to Revision 0.4
Updated Figure 1.
Updated Digital Supply Voltage in Table 2.
Updated Figure 3.
Revision 0.4 to Revision 1.0
Updated CS and INT to have the overbar in Section
4.1.
Added VRST parameter to Table 1 on page 4.
Updated the description of Register 7, “IOCONFIG:
Port I/O Configuration,” on page 19 to describe 11b
as Reserved.
Added a note regarding no repeated start support in
Section 6 on page 13.
Added a note regarding SPI clock speeds to Section
5 on page 9.
Rev. 1.0
CP2120
23
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