CP2120 Ver la hoja de datos (PDF) - Silicon Laboratories

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CP2120

SPI TO I2C BRIDGE AND GPIO PORT EXPANDER

Silicon Laboratories 

CP2120

Internal Register Definition 5. I2CSTAT: I2C Status Register

R

I2ST7

Bit 7

R

I2ST6

Bit 6

R

I2ST5

Bit 5

R

I2ST4

Bit 4

R

I2ST3

Bit3

R

I2ST2

Bit 2

R

I2ST1

Bit 1

R

I2ST0

Bit 0

Internal Register Address: 0x04

Reset Value: 0x00

Bit 7–0

I2ST: I2C Status

I2C Status Value

Status Description

0xF0

I2C transaction completed successfully.

0xF1

Slave address NACKed.

0xF2

0xF3

0xF8

Slave data NACKed.

I2C transaction in progress.

I2C transaction timed out due to timer configured in I2CTO.

0xF9

0xFA

0xFB

Command’s Bytes to Transmit Byte and Data Buffer Size do not match, or Read Buf-

fer read number of bytes greater than buffer count.

I2C SCL Low time-out, using timer configured in I2CTO2.

I2C bus free detect has been disabled, and the bus is not free.

16

Rev. 1.0

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