DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

CM3205 Ver la hoja de datos (PDF) - California Micro Devices Corp

Número de pieza
componentes Descripción
Fabricante
CM3205
CALMIRCO
California Micro Devices Corp CALMIRCO
CM3205 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
PRELIMINARY
CM3205
Application Information (cont’d)
The VTT power requirement is proportional to the num-
ber of data lines and the resistance of the termination
resistor, but does not vary with memory size. In a typi-
cal DDR data bus system each data line termination
may momentarily consume 16.2-mA to achieve the
405-mV minimum over VTT needed at the receiver:
Iterminaton
=
--4---0---5----m-----V----
R t ( 25 Ω )
=
16.2mA
A typical 128 Mbyte SSTL-2 memory system, with 192
terminated lines, has a worst-case maximum VTT sup-
ply current up to ±3.11A. However, a DDR memory
system is dynamic, and the theoretical peak currents
only occur for short durations, if they ever occur at all.
These high current peaks can be handled by the VTT
external capacitor. In a real memory system, the con-
tinuous average VTT current level in normal operation
is less than ±200 mA.
The VDDQ power supply, in addition to supplying cur-
rent to the memory banks, could also supply current to
controllers and other circuitry. The current level typi-
cally stays within a range of 2.0A to 3.0A, with peaks
up to 4.0A or more, depending on memory size and the
computing operations being performed.
The tight tracking requirements and the need for VTT to
sink, as well as source, current provide unique chal-
lenges for powering DDR SDRAM.
CM3205 Regulator
The CM3205 dual output linear regulator provides all of
the power requirements of DDR memory by combining
two linear regulators into a single TO-263 or TO-252 5-
lead package. The VDDQ regulator can supply up to 5A
continuous current, and the two-quadrant VTT termina-
tion regulator has current sink and source capability to
±2A. The VDDQ linear regulator uses a PMOS pass
element for a very low dropout voltage, typically 600mV
at a 5A output. The output voltage of the VDDQ regula-
tor can be set by an external voltage divider. The sec-
ond output, VTT, is regulated at VDDQ/2 by an internal
resistor divider. The VTT regulator can source, as well
as sink, up to 2A continuous current. The CM3205 is
designed for optimal operation from a nominal 3.3VDC
bus, but can work with VIN as high as 5V. When operat-
ing at higher VIN voltages, attention must be given to
the increased package power dissipation and propor-
tionally increased heat generation.
VREF is typically routed to inputs with high impedance,
such as a comparator, with little current draw. An ade-
quate VREF can be created with a simple voltage
divider of precision, matched resistors from VDDQ to
ground. A small ceramic bypass capacitor can also be
added for improved noise performance.
Input and Output Capacitors
The CM3205 requires that at least a 680μF electrolytic
capacitor be located near the VIN pin for stability and to
maintain the input bus voltage during load transients.
An additional 4.7μF ceramic capacitor between the VIN
(pin 4) and the GND (pin 5), located as close as possi-
ble to those pins, is recommended to ensure stability.
A minimum of a 680μF electrolytic capacitor is recom-
mended for the VDDQ output. An additional 4.7μF
ceramic capacitor between the VDDQ (pin 2) and GND,
located very close to those pins, is recommended.
A minimum of a 680μF, electrolytic capacitor is recom-
mended for the VTT output. This capacitor should have
low ESR to achieve best output transient response. SP
or OSCON capacitors provide low ESR at high fre-
quency, and thus are a good choice. In addition, place
a 4.7μF ceramic capacitor between the VTT pin (pin 5)
and GND, located very close to those pins. The total
ESR must be low enough to keep the transient within
the VTT window of 40-mV during the transition for
source to sink. An average current step of ±0.5A
requires:
ESR
<
4----0---m-----V---
1A
=
40mΩ
Both outputs will remain stable and in regulation even
during light or no load conditions.
Adjusting VDDQ Output Voltage
The CM3205 internal bandgap reference is set at
1.215V. The VDDQ voltage is adjustable by using a
resistor divider, R1 and R2:
VOUT
=
VA
D
J
×
1
+
RR-----21-⎠⎞
© 2006 California Micro Devices Corp. All rights reserved.
05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 l Tel: 408.263.3214 l Fax: 408.263.7846 l www.cmd.com
7

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]