CS42L51(2005) Ver la hoja de datos (PDF) - Cirrus Logic
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CS42L51 Datasheet PDF : 83 Pages
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CS42L51
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 13))
Frequency Response 10 Hz to 20 kHz
Passband
StopBand
StopBand Attenuation (Note 14)
Group Delay
De-emphasis Error
Min
Typ
Max Unit
-0.01
-
+0.08
dB
to -0.05 dB corner 0
to -3 dB corner 0
-
0.4780 Fs
-
0.4996 Fs
0.5465
-
-
Fs
50
-
-
dB
-
9/Fs
-
s
Fs = 32 kHz -
Fs = 44.1 kHz -
Fs = 48 kHz -
-
+1.5/+0 dB
-
+0.05/-0.25 dB
-
-0.2/-0.4 dB
Notes:
13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 35 and 36 on
page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
14. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)
RESET pin Low Pulse Width
MCLK Frequency
MCLK Duty Cycle
Slave Mode
Input Sample Rate (LRCK)
Parameters
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Symbol
(Note 15)
(Note 16)
Min
1
1.024
45
Quarter-Speed Mode Fs
4
Half-Speed Mode Fs
8
Single-Speed Mode Fs
4
Double-Speed Mode Fs
50
45
1/tP
-
45
ts(LK-SK)
40
td(MSB)
-
ts(SDO-SK)
30
th(SK-SDO)
30
ts(SD-SK)
20
th
20
Max
-
38.4
55
Units
ms
MHz
%
12.5
kHz
25
kHz
50
kHz
100
kHz
55
%
64•Fs
Hz
55
%
-
ns
40
ns
-
ns
-
ns
-
ns
-
ns
20
DS679A2
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