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CBT3857 Ver la hoja de datos (PDF) - Philips Electronics

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Fabricante
CBT3857 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Philips Semiconductors
10-bit bus switch with 10 kpull-down
termination resistors
Product specification
CBT3857
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = 0°C to +85°C
Min
Typ1
Max
UNIT
VIK
Input clamp voltage
II
Input leakage current
VCC = 3 V; II = –18 mA
VCC = 3.6 V; VI = VCC or GND
OE
A Port
B Port
–1.2
V
±0.73
±500
µA
±0.1
±1
µA
±20
±500
µA
VREF
±0.1
±1
µA
ICC
Quiescent supply current
VCC = 3.6 V; IO = 0, VI = VCC or GND
0.7
1.5
mA
CI
Control pins
VI= 3 V or 0
2.8
pF
CiO(OFF) Power-off leakage current
VO = 3 V or 0; OE = VCC
6.4
pF
VCC = 3 V to 3.6 V; VA = 0.8 V; VB = 1.15 V
20
24
30
ron2
On-resistance
VCC = 3 V to 3.6 V; VA = 1.7 V; VB = 1.35 V
20
24
30
roff2
Off-resistance
VCC = 3 V to 3.6 V; VI = 1.25 V; II = ±10 mA
VCC = 3 V to 3.6 V; VI = 1.65 V
20
24
30
1
M
NOTES:
1. All typical values are at VCC = 3.3 V, Tamb = 25°C
2. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On–state resistance is
determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
SYMBOL
PARAMETER
FROM (INPUT) TO (OUTPUT)
VCC = +3.3 V ±0.3 V
Min
Max
UNIT
tpd
Propagation delay1
A or B
B or A
750
ps
ten
enable
OE
A or B
1
3
ns
tdis
disable
OE
A or B
1
3
ns
NOTE:
1. The propagation delay is based on the RC time constant of the typical on–state resistance of the switch and a load capacitance, when driven
by an ideal voltage source (zero output impedance); 24 × 30 pF.
184/200-pin DDR SDRAM DIMM
BACK SIDE
CBT CBT
CBT CBT
CBT
CBT
CBT
CBT CBT
CBT3857 (9)
FRONT SIDE
1999 Sep 14
SSTL16857 SSTL16857
PCK857
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00393
4

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