CAT1021 Ver la hoja de datos (PDF) - ON Semiconductor

Número de pieza

componentes Descripción

Fabricante

CAT1021

Supervisory Circuits with EEPROM Serial 2k-bit I2C Manual Reset and Watchdog Timer

ON Semiconductor 

CAT1021, CAT1022, CAT1023

S

T

S

BUS  ACTIVIT Y: A

SL AVE

T

MASTER R ADDRESS

O

T

P

SD A LINE S

P

A

N

C

DATA

O

K

A

C

K

SC L

8

9

SD A             8TH BI T

DATA OU T

NO ACK

Figure 10. Immediate Address Read Timing

STOP

Immediate/Current Address Read

The CAT1021/22/23 address counter contains the address

of the last byte accessed, incremented by one. In other

words, if the last READ or WRITE access was to address N,

the READ immediately following would access data from

address N + 1. For N = E = 255, the counter will wrap around

to zero and continue to clock out valid data. After the

CAT1021/22/23 receives its slave address information (with

the R/W bit set to one), it issues an acknowledge, then

transmits the 8−bit byte requested. The master device does

not send an acknowledge, but will generate a STOP

condition.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte addresses of the location it wishes to read.

After the CAT1021/22/23 acknowledges, the Master device

sends the START condition and the slave address again, this

time with the R/W bit set to one. The CAT1021/22/23 then

responds with its acknowledge and sends the 8−bit byte

requested. The master device does not send an acknowledge

but will generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by either

the Immediate Address READ or Selective READ

operations. After the CAT1021/22/23 sends the inital 8− bit

byte requested, the Master will responds with an

acknowledge which tells the device it requires more data.

The CAT1021/22/23 will continue to output an 8− bit byte

for each acknowledge, thus sending the STOP condition.

The data being transmitted from the CAT1021/22/23 is

sent sequentially with the data from address N followed by

data from address N + 1. The READ operation address

counter increments all of the CAT1021/22/23 address bits so

that the entire memory array can be read during one

operation.

S

T

BUS ACTIVITY: A

MASTER R

T

SDA LINE S

SLAVE

ADDRESS

BYTE

ADDRESS (n)

S

T

A

SLAVE

R ADDRESS

T

S

A

A

A

C

C

C

K

K

K

Figure 11. Selective Read Timing

S

T

O

P

P

N

DATA n O

A

C

K

www.onsemi.com

12

Share Link: