CAT1021(2004) Ver la hoja de datos (PDF) - Catalyst Semiconductor => Onsemi

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CAT1021
(Rev.:2004)

Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer

Catalyst Semiconductor => Onsemi 

CAT1021, CAT1022, CAT1023

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write opration, the

CAT1021/22/23 initiates the internal write cycle. ACK

polling can be initiated immediately. This involves issuing

the start condition followed by the slave address for a

write operation. If the device is still busy with the write

operation, no ACK will be returned. If a write operation

has completed, an ACK will be returned and the host can

then proceed with the next read or write operation.

WRITE PROTECTION PIN (WP)

The Write Protection feature (CAT1021 only) allows the

user to protect against inadvertent memory array

programming. If the WP pin is tied to VCC, the entire

memory array is protected and becomes read only. The

CAT1021 will accept both slave and byte addresses,

but the memory location accessed is protected from

programming by the device’s failure to send an

acknowledge after the first byte of data is received.

Read Operations

The READ operation for the CAT1021/22/23 is initiated

in the same manner as the write operation with one

exception, the R/W bit is set to one. Three different

READ operations are possible: Immediate/Current

Address READ, Selective/Random READ and

Sequential READ.

Figure 10. Immediate Address Read Timing

SCL

SDA

S

T

S

BUS ACTIVITY: A

SLAVE

T

MASTER R ADDRESS

O

T

P

SDA LINE S

P

A

N

C

DATA

O

K

A

C

K

8

9

8TH BIT

DATA OUT

NO ACK

STOP

Doc. No. 3009, Rev. K

12

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