C8051F326 Ver la hoja de datos (PDF) - Unspecified

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Fabricante

C8051F326

Full Speed USB, 16 kB Flash MCU Family

Unspecified 

C8051F326/7

1.3. Universal Serial Bus Controller

The Universal Serial Bus Controller (USB0) is a USB 2.0 peripheral with integrated transceiver and end-

point FIFO RAM. The controller supports both full and low speed modes. A total of three endpoint pipes are

available: a bi-directional control endpoint (Endpoint0) and a data endpoint (Endpoint1) with one IN pipe

and one OUT pipe.

A 256 block of XRAM is used as dedicated USB FIFO space. This FIFO space is distributed between

Endpoint0 and Endpoint1. Endpoint0 is 64 bytes, and Endpoint1 has a 64 byte IN pipe and a 128 byte OUT

pipe.

USB0 can be operated as a Full or Low Speed function. The on-chip 4x Clock Multiplier and clock recovery

circuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as

the USB clock source. An external clock source can also be used with the 4x Clock Multiplier to generate

the USB clock.

The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pullup resistors. The pul-

lup resistors can be enabled/disabled in software, and will appear on the D+ or D– pin according to the

software-selected speed setting (full or low speed).

Transceiver

VDD

D+

D-

Serial Interface Engine (SIE)

Endpoint0

Data

Transfer

Control

IN/OUT

Endpoint1

IN

OUT

USB

Control,

Status, and

Interrupt

Registers

CIP-51 Core

USB FIFOs

(256B RAM)

Figure 1.6. USB Controller Block Diagram

1.4. Voltage Regulator

C8051F326/7 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on

the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software.

Rev. 0.5

19

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