C167CR Ver la hoja de datos (PDF) - Siemens AG

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componentes Descripción

Fabricante

C167CR

16-Bit CMOS Single-Chip Microcontroller

Siemens AG 

C167CR

The C167CR also provides an excellent mechanism to identify and to process exceptions or error

conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate

non-maskable system reaction which is similar to a standard interrupt service (branching to a

dedicated vector table location). The occurrence of a hardware trap is additionally signified by an

individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in

progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap

services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run-

time:

Exception Condition

Reset Functions:

Hardware Reset

Software Reset

Watchdog Timer Overflow

Class A Hardware Traps:

Non-Maskable Interrupt

Stack Overflow

Stack Underflow

Class B Hardware Traps:

Undefined Opcode

Protected Instruction

Fault

Illegal Word Operand

Access

Illegal Instruction Access

Illegal External Bus

Access

Reserved

Software Traps

TRAP Instruction

Trap

Flag

Trap

Vector

Vector

Location

Trap

Number

Trap

Priority

RESET 00’0000H 00H

III

RESET 00’0000H 00H

III

RESET 00’0000H 00H

III

NMI

NMITRAP 00’0008H 02H

II

STKOF STOTRAP 00’0010H 04H

II

STKUF STUTRAP 00’0018H 06H

II

UNDOPC BTRAP 00’0028H 0AH

I

PRTFLT BTRAP 00’0028H 0AH

I

ILLOPA BTRAP 00’0028H 0AH

I

ILLINA

BTRAP 00’0028H 0AH

I

ILLBUS BTRAP 00’0028H 0AH

I

[2CH – 3CH]

Any

[00’0000H –

00’01FCH]

in steps

of 4H

[0BH – 0FH]

Any

[00H – 7FH]

Current

CPU

Priority

Semiconductor Group

18

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