AS4LC1M16S1-10TC Ver la hoja de datos (PDF) - Alliance Semiconductor

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componentes Descripción

Fabricante

AS4LC1M16S1-10TC

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

Self refresh waveform

CLK

CS

RAS

CAS

WE

A11

A0–A10

DQM

CKE

DQ

Precharge

both

banks

Self

refresh

Self refresh

entry cycle

Self refresh exit

tRC

Clock stable before

self refresh exit

Power down mode waveform

CLK

CS

RAS

Arbitrary cycle

CAS

WE

A11

A10

RAa

A0–A9

RAa

CAa

DQM

RAa

RAa

CAx

CKE

DQ

Bank activate

Active standby

Power down mode

NOP

Data burst

Precharge standby

Power down mode

NOP Bank activate

Power down mode entry

Power down mode exit Power down mode entry

Enter power down mode by pulling CKE low.

All input/output buffers (except CKE buffer) are turned off in power down mode.

When CKE goes high, command input must be equal to no operation at next CLK rising edge.

Power down mode exit

(CL = 3)

7/5/00

ALLIANCE SEMICONDUCTOR

23

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