AS4LC1M16S1(2000) Ver la hoja de datos (PDF) - Alliance Semiconductor

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componentes Descripción

Fabricante

AS4LC1M16S1
(Rev.:2000)

3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC2M8S1

AS4LC1M16S1

Burst stop command waveform

CLK

read cycle

tT

CMD

DQ (CL = 1)

DQ (CL = 2)

DQ (CL = 3)

Read data

tOH

Q0

Burst stop

Q1

Q2

Q0

Q1

Q2

Q0

Q1

Q2

write cycle (BL = 8)

CLK

CMD

DQ

(CL = 1,2,3)

Write data

DQ

D1

Burst stop

D2

D3

Precharge termination

A Precharge command terminates a burst read/write operation during the read cycle. The same bank can be activated after meeting tRP. If an

RD-burst is terminated, o/p will go to High Z after the number of cycles = CAS latency.

read cycle (CL = 1)

CLK

CMD

DQ

Read data

PRE

ACT

Q0

Q1

Q2

Q3

tRP

read cycle (CL = 2)

CLK

CMD

DQ

Read data

tRP

PRE

ACT

Q0

Q1

Q2

Q3

tROH (CL = 2)

CLK

CMD

DQ

Read data

read cycle (CL = 3)

tRP

PRE

ACT

Q0

Q1

Q2

Q3

tROH (CL = 3)

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